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general description the max5522?ax5525 are dual, 10-bit, ultra-low- power, voltage-output, digital-to-analog converters (dacs) offering rail-to-rail buffered voltage outputs. the dacs operate from a 1.8v to 5.5v supply and con- sume less than 5?, making the devices suitable for low-power and low-voltage applications. a shutdown mode reduces overall current, including the reference input current, to just 0.18?. the max5522?ax5525 use a 3-wire serial interface that is compatible with spi, qspi, and microwire. upon power-up, the max5522?ax5525 outputs are driven to zero scale, providing additional safety for applications that drive valves or for other transducers that need to be off during power-up. the zero-scale outputs enable glitch-free power-up. the max5522 accepts an external reference input and provides unity-gain outputs. the max5523 contains a precision internal reference and provides a buffered external reference output with unity-gain dac outputs. the MAX5524 accepts an external reference input and provides force-sense outputs. the max5525 contains a precision internal reference and provides a buffered external reference output with force-sense dac outputs. the max5522 is pin-for-pin compatible with the ltc1662. the MAX5524/max5525 are available in a 4mm x 4mm x 0.8mm, 12-pin, thin qfn package. the max5522/ max5523 are available in an 8-pin ?ax package. all devices are guaranteed over the extended -40? to +85? temperature range. for 12-bit compatible devices, refer to the max5532 max5535 data sheet. for 8-bit compatible devices, refer to the max5512?ax5515 data sheet. applications portable battery-powered devices instrumentation automatic trimming and calibration in factory or field programmable voltage and current sources industrial process control and remote industrial devices remote data conversion and monitoring chemical sensor cell bias for gas monitors programmable lcd bias features ? ultra-low 5? supply current ? shutdown mode reduces supply current to 0.18? (max) ? single +1.8v to +5.5v supply ? small 4mm x 4mm x 0.8mm thin qfn package ? internal reference sources 8ma of current (max5523/max5525) ? flexible force-sense-configured rail-to-rail output buffers ? fast 16mhz, 3-wire, spi-/qspi-/microwire- compatible serial interface ? ttl- and cmos-compatible digital inputs with hysteresis ? glitch-free outputs during power-up ? the max5522 is pin-for-pin compatible with the ltc1662 max5522?ax5525 dual, ultra-low-power, 10-bit, voltage-output dacs ________________________________________________________________ maxim integrated products 1 ordering information 19-3064; rev 0; 1/04 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. * ep = exposed paddle (internally connected to gnd). part temp range pin-package max5522 eua -40? to +85? 8 ?ax max5523 eua -40? to +85? 8 ?ax MAX5524 etc -40? to +85? 12 thin qfn-ep* max5525 etc -40? to +85? 12 thin qfn-ep* rail-to-rail is a registered trademark of nippon motorola, inc. spi and qspi are trademarks of motorola, inc. microwire is a trademark of national semiconductor corp. selector guide part outputs reference top mark max5522eua unity gain external max5523eua unity gain internal MAX5524etc force sense external aack max5525etc force sense internal aacl 1 2 3 4 8 7 6 5 outa gnd v dd outb refin(max5522) refout(max5523) din sclk cs max5522 max5523 max top view pin configurations pin configurations continued at end of data sheet.
max5522?ax5525 dual, ultra-low-power, 10-bit, voltage-output dacs 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (v dd = +1.8v to +5.5v, out_ unloaded, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v dd to gnd ..............................................................-0.3v to +6v outa, outb to gnd .................................-0.3v to (v dd + 0.3v) fba, fbb to gnd .......................................-0.3v to (v dd + 0.3v) sclk, din, cs to gnd ..............................-0.3v to (v dd + 0.3v) refin, refout to gnd ............................-0.3v to (v dd + 0.3v) continuous power dissipation (t a = +70?) 12-pin thin qfn (derate 16.9mw/c above +70c).....1349mw 8-pin ?ax (derate 5.9mw/? above +70?) .............471mw operating temperature range ...........................-40? to +85? storage temperature range .............................-65? to +150? junction temperature ......................................................+150? lead temperature (soldering, 10s) .................................+300? parameter symbol conditions min typ max units static accuracy (max5522/MAX5524 external reference) resolution n 10 bits v dd = 5v, v ref = 4.096v 1 4 integral nonlinearity (note 1) inl v dd = 1.8v, v ref = 1.024v 1 4 lsb guaranteed monotonic, v dd = 5v, v ref = 4.096v 0.2 1 differential nonlinearity (note 1) dnl guaranteed monotonic, v dd = 1.8v, v ref = 1.024v 0.2 1 lsb v dd = 5v, v ref = 4.096v 1 20 offset error (note 2) v os v dd = 1.8v, v ref = 1.024v 1 20 mv offset-error temperature drift 2 ?/ c v dd = 5v, v ref = 4.096v 0.5 2 gain error (note 3) ge v dd = 1.8v, v ref = 1.024v 0.5 2 lsb gain-error temperature coefficient 4 ppm/ c power-supply rejection ratio psrr 1.8v v dd 5.5v 85 db static accuracy (max5523/max5525 internal reference) resolution n 10 bits v dd = 5v, v ref = 3.9v 1 4 integral nonlinearity (note 1) inl v dd = 1.8v, v ref = 1.2v 1 4 lsb guaranteed monotonic, v dd = 5v, v ref = 3.9v 0.2 1 differential nonlinearity (note 1) dnl guaranteed monotonic, v dd = 1.8v, v ref = 1.2v 0.2 1 lsb v dd = 5v, v ref = 3.9v 1 20 offset error (note 2) v os v dd = 1.8v, v ref = 1.2v 1 20 mv offset-error temperature drift 2 ?/ c v dd = 5v, v ref = 3.9v 0.5 2 gain error (note 3) ge v dd = 1.8v, v ref = 1.2v 0.5 2 lsb gain-error temperature coefficient 4 ppm/ c
max5522?ax5525 dual, ultra-low-power, 10-bit, voltage-output dacs _______________________________________________________________________________________ 3 electrical characteristics (continued) (v dd = +1.8v to +5.5v, out_ unloaded, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) parameter symbol conditions min typ max units power-supply rejection ratio psrr 1.8v v dd 5.5v 85 db reference input (max5522/MAX5524) reference-input voltage range v refin 0v dd v normal operation 4.1 m ? reference-input impedance r refin in shutdown 2.5 g ? reference output (max5523/max5525) no external load, v dd = 1.8v 1.197 1.214 1.231 no external load, v dd = 2.5v 1.913 1.940 1.967 no external load, v dd = 3v 2.391 2.425 2.459 initial accuracy v refout no external load, v dd = 5v 3.828 3.885 3.941 v output-voltage temperature coefficient v tempco t a = -40 c to +85 c (note 4) 12 30 ppm/ c line regulation v refout < v dd - 200mv (note 5) 2 200 ?/v 0 i refout 1ma, sourcing, v dd = 1.8v, v ref = 1.2v 0.3 2 0 i refout 8ma, sourcing, v dd = 5v, v ref = 3.9v 0.3 2 load regulation -150? i refout 0, sinking 0.2 ?/? 0.1hz to 10hz, v ref = 3.9v 150 10hz to 10khz, v ref = 3.9v 600 0.1hz to 10hz, v ref = 1.2v 50 output noise voltage 10hz to 10khz, v ref = 1.2v 450 ? p-p v dd = 5v 30 short-circuit current (note 6) v dd = 1.8v 14 ma capacitive load stability range (note 7) 0 to 10 nf thermal hysteresis (note 8) 200 ppm refout unloaded, v dd = 5v 5.4 reference power-up time (from shutdown) refout unloaded, v dd = 1.8v 4.4 ms long-term stability 200 ppm/ 1khrs dac outputs (outa, outb) capacitive driving capability c l 1000 pf v dd = 5v, v out set to full scale, out shorted to gnd, source current 65 v dd = 5v v out set to 0v, out shorted to v dd , sink current 65 v dd = 1.8v, v out set to full scale out shorted to gnd, source current 14 short-circuit current (note 6) v dd = 1.8v, v out set to 0v, out shorted to v dd , sink current 14 ma
max5522?ax5525 dual, ultra-low-power, 10-bit, voltage-output dacs 4 _______________________________________________________________________________________ electrical characteristics (continued) (v dd = +1.8v to +5.5v, out_ unloaded, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) parameter symbol conditions min typ max units v dd = 5v 3 coming out of shutdown (max5522/MAX5524) v dd = 1.8v 3.8 dac power-up time coming out of standby (max5523/max5525) v dd = 1.8v to 5.5v 0.4 ? output power-up glitch c l = 100pf 10 mv fb_ input current 10 pa digital inputs (sclk, din, cs ) 4.5v v dd 5.5v 2.4 2.7v < v dd 3.6v 2.0 input high voltage v ih 1.8v v dd 2.7v 0.7 x v dd v 4.5v v dd 5.5v 0.8 2.7v < v dd 3.6v 0.6 input low voltage v il 1.8v v dd 2.7v 0.3 x v dd v input leakage current i in (note 9) 0.05 0.5 ? input capacitance c in 10 pf dynamic performance voltage-output slew rate sr positive and negative (note 10) 10 v/ms voltage-output settling time 0.1 to 0.9 of full scale to within 0.5 lsb (note 10) 660 ? v dd = 5v 80 0.1hz to 10hz v dd = 1.8v 55 v dd = 5v 620 output noise voltage 10hz to 10khz v dd = 1.8v 476 ? p-p power requirements supply voltage range v dd 1.8 5.5 v v dd = 5v 7.0 8.0 v dd = 3v 6.4 8.0 max5523/max5525 v dd = 1.8v 7.0 8.0 v dd = 5v 3.8 5.0 v dd = 3v 3.8 5.0 supply current (note 9) i dd max5522/MAX5524 v dd = 1.8v 4.7 6.0 ? v dd = 5v 3.3 4.5 v dd = 3v 2.8 4.0 standby supply current i ddsd max5523/max5525 (note 9) v dd = 1.8v 2.4 3.5 ? shutdown supply current i ddpd (note 9) 0.05 0.25 ?
max5522?ax5525 dual, ultra-low-power, 10-bit, voltage-output dacs _______________________________________________________________________________________ 5 note 1: linearity is tested within codes 24 to 1020. note 2: offset is tested at code 24. note 3: gain is tested at code 1023. for the MAX5524/max5525, fb_ is connected to its respective out_. note 4: guaranteed by design. not production testsed note 5: v dd must be a minimum of 1.8v. note 6: outputs can be shorted to v dd or gnd indefinitely, provided that package power dissipation is not exceeded. note 7: optimal noise performance is at 2nf load capacitance. note 8: thermal hysteresis is defined as the change in the initial +25? output voltage after cycling the device from t max to t min . note 9: all digital inputs at v dd or gnd. note 10: load = 10k ? in parallel with 100pf, v dd = 5v, v ref = 4.096v (max5522/MAX5524) or v ref = 3.9v (max5523/max5525). timing characteristics (v dd = +4.5v to +5.5v, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) parameter symbol conditions min typ max units timing characteristics (v dd = 4.5v to 5.5v ) serial clock frequency f sclk 0 16.7 mhz din to sclk rise setup time t ds 15 ns din to sclk rise hold time t dh 0ns sclk pulse-width high t ch 24 ns sclk pulse-width low t cl 24 ns cs pulse-width high t csw 100 ns sclk rise to cs rise hold time t csh 0ns cs fall to sclk rise setup time t css 20 ns sclk fall to cs fall setup t cso 0ns cs rise to sck rise hold time t cs1 20 ns timing characteristics (v dd = +1.8v to +5.5v, t a = t min to t max , unless otherwise noted. typical values are at t a = +25 c.) parameter symbol conditions min typ max units timing characteristics (v dd = 1.8v to 5.5v ) serial clock frequency f sclk 010mhz din to sclk rise setup time t ds 24 ns din to sclk rise hold time t dh 0ns sclk pulse-width high t ch 40 ns sclk pulse-width low t cl 40 ns cs pulse-width high t csw 150 ns sclk rise to cs rise hold time t csh 0ns cs fall to sclk rise setup time t css 30 ns sclk fall to cs fall setup t cso 0ns cs rise to sck rise hold time t cs1 30 ns
max5522?ax5525 dual, ultra-low-power, 10-bit, voltage-output dacs 6 _______________________________________________________________________________________ t ypical operating characteristics (v dd = 5.0v, v ref = 4.096v (max5522/MAX5524), vref = 3.9v (max5523/max54525), t a = +25?, unless otherwise noted.) supply current vs. supply voltage (max5522/MAX5524) max5522 toc01 supply voltage (v) supply current ( a) 5.5 5.0 4.0 4.5 2.5 3.0 3.5 2.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0 1.5 6.0 supply current vs. temperature (max5522/MAX5524) max5522 toc02 temperature ( c) supply current ( a) 60 35 10 -15 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0 -40 85 supply current vs. supply voltage (max5523/max5525) max5522 toc03 supply voltage (v) supply current ( a) 5.5 5.0 4.0 4.5 2.5 3.0 3.5 2.0 1 2 3 4 5 6 7 8 9 10 0 1.5 6.0 supply current vs. temperature (max5523/max5525) max5522 toc04 temperature ( c) supply current ( a) 60 35 10 -15 1 2 3 4 5 6 7 8 9 10 0 -40 85 shutdown supply current vs. temperature (max5522/MAX5524) max5522 toc05 temperature ( c) shutdown supply current (na) 60 35 10 -15 1 10 100 1000 0.1 -40 85 shutdown supply current vs. temperature (max5523/max5525) max5522 toc06 temperature ( c) shutdown supply current (na) 60 35 10 -15 1 10 100 1000 0.1 -40 85 standby supply current vs. temperature (max5523/max5525) max5522 toc07 temperature ( c) standby supply current ( a) 60 35 10 -15 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0 -40 85 v ref = 3.9v v ref = 2.4v v ref = 1.9v v ref = 1.2v supply current vs. clock frequency max5522 toc08 frequency (khz) supply current ( a) 10000 1000 100 10 1 0.1 10 100 1000 1 0.01 100000 cs = logic low code = 0 v dd = 5v v dd = 1.8v supply current vs. logic input voltage max5522 toc09 logic input voltage (v) supply current (ma) 4.5 4.0 3.0 3.5 1.0 1.5 2.0 2.5 0.5 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0 05.0 v dd = 5v all digital inputs shorted together
max5522?ax5525 dual, ultra-low-power, 10-bit, voltage-output dacs _______________________________________________________________________________________ 7 inl vs. input code (v dd = v ref = 1.8v) max5522 toc10 digital input code inl (lsb) 1000 800 200 400 600 -1.0 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 -1.2 0 1200 inl vs. input code (v dd = v ref = 5v) max5522 toc11 digital input code inl (lsb) 1000 800 200 400 600 -1.0 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 -1.2 01200 dnl vs. input code (v dd = v ref = 1.8v) max5522 toc12 digital input code dnl (lsb) 1000 800 600 400 200 -0.02 -0.01 0 0.01 0.02 0.03 0.04 0.05 0.06 -0.03 0 1200 dnl vs. input code (v dd = v ref = 5v) max5522 toc13 digital input code dnl (lsb) 1000 800 600 400 200 -0.02 -0.01 0 0.01 0.02 0.03 0.04 -0.03 0 1200 offset voltage vs. temperature max5522 toc14 temperature ( c) offset voltage (mv) 60 35 10 -15 0.2 0.4 0.6 0.8 1.0 -1.0 -0.2 0 -40 85 -0.4 -0.6 -0.8 v dd = 5v v ref = 3.9v gain error change vs. temperature max5522 toc15 temperature ( c) gain error change (lsb) 60 35 10 -15 -0.08 -0.06 -0.04 -0.02 0 0.02 0.04 0.06 0.08 0.10 -0.10 -40 85 v dd = 5v v ref = 3.9v digital feedthrough response max5522 toc16 20 s/div cs 5v/div sclk 5v/div din 5v/div out 50mv/div zero scale dac output load regulation vs. output current max5522 toc17 dac output current ( a ) dac output voltage (v) 800 600 400 200 0 -200 -400 -600 -800 0.6042 0.6044 0.6046 0.6048 0.6050 0.6040 -1000 1000 v dd = 1.8v dac code = midscale v ref = 1.2v dac output load regulation vs. output current max5522 toc18 dac output current (ma) dac output voltage (v) 8 6 -8 -6 -4 0 2 -2 4 1.9405 1.9410 1.9415 1.9420 1.9425 1.9430 1.9435 1.9440 1.9400 -10 10 v dd = 5.0v dac code = midscale v ref = 3.9v t ypical operating characteristics (continued) (v dd = 5.0v, v ref = 4.096v (max5522/MAX5524), vref = 3.9v (max5523/max54525), t a = +25?, unless otherwise noted.)
max5522?ax5525 dual, ultra-low-power, 10-bit, voltage-output dacs 8 _______________________________________________________________________________________ t ypical operating characteristics (continued) (v dd = 5.0v, v ref = 4.096v (max5522/MAX5524), vref = 3.9v (max5523/max54525), t a = +25?, unless otherwise noted.) dac output voltage vs. output source current max5522 toc19 output source current (ma) output voltage (v) 10 1 0.100 0.010 1 2 3 4 5 0 0.001 100 v ref = v dd code = midscale v dd = 5v v dd = 3v v dd = 1.8v dac output voltage vs. output sink current max5522 toc20 output sink current (ma) dac output voltage (v) 10 1 0.1 0.01 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0 0.001 100 v ref = v dd code = midscale v dd = 5v v dd = 3v v dd = 1.8v output large-signal step response (v dd = 1.8v, v ref = 1.2v) max5522 toc21 100 s/div v out 200mv/div output large-signal step response (v dd = 5v, v ref = 3.9v) max5522 toc22 200 s/div v out 500mv/div output minimum series resistance vs. load capacitance max5522 toc23 capacitance ( f) minimum series resistance ( ? ) 10 1 0.1 0.01 0.001 100 200 300 400 500 600 0 0.0001 100 for no overshoot power-up output voltage glitch max5522 toc24 20ms/div v out 10mv/div v dd 2v/div major carry output voltage glitch (code 7ffh to 800h) (v dd = 5v, v ref = 3.9v) max5522 toc25 100 s/div v out ac-coupled 5mv/div reference output voltage vs. temperature max5522 toc26 temperature ( c) reference output voltage (v) 60 35 -15 10 3.905 3.910 3.915 3.920 3.925 3.930 3.935 3.940 3.900 -40 85 v dd = 5v reference output voltage vs. reference output current max5522 toc27 reference output current ( a) reference output voltage (v) 7500 5500 3500 1500 1.215 1.216 1.217 1.218 1.219 1.220 1.214 -500 v dd = 1.8v
max5522?ax5525 dual, ultra-low-power, 10-bit, voltage-output dacs _______________________________________________________________________________________ 9 t ypical operating characteristics (continued) (v dd = 5.0v, v ref = 4.096v (max5522/MAX5524), vref = 3.9v (max5523/max54525), t a = +25?, unless otherwise noted.) reference output voltage vs. reference output current max5522 toc28 reference output current ( a) reference output voltage (v) 14,500 12,000 9500 7000 4500 2000 3.89 3.90 3.91 3.92 3.88 -500 v dd = 5v reference output voltage vs. supply voltage max5522 toc29 supply voltage (v) reference output voltage (mv) 5.5 5.0 4.0 4.5 2.5 3.0 3.5 2.0 1.21732 1.21734 1.21736 1.21738 1.21740 1.21742 1.21744 1.21746 1.21748 1.21750 1.21730 1.5 6.0 reference line-transient response (v ref = 1.2v) max5522 toc30 100 s/div 2.8v v dd 1.8v v ref 500mv/div reference line-transient response (v ref = 3.9v) max5522 toc31 100 s/div 5.5v v dd 4.5v v ref 500mv/div 3.9v reference load transient (v dd = 1.8v) max5522 toc32 200 s/div refout source current 0.5ma/div v ref 500mv/div reference load transient (v dd = 5v) max5522 toc33 200 s/div refout source current 0.5ma/div v ref 500mv/div 3.9v reference load transient (v dd = 1.8v) max5522 toc34 200 s/div refout sink current 50 a/div v ref 500mv/div
max5522?ax5525 dual, ultra-low-power, 10-bit, voltage-output dacs 10 ______________________________________________________________________________________ t ypical operating characteristics (continued) (v dd = 5.0v, v ref = 4.096v (max5522/MAX5524), vref = 3.9v (max5523/max54525), t a = +25?, unless otherwise noted.) reference psrr vs. frequency max5522 toc37 frequency (khz) power-supply rejection ratio (db) 100 10 0.1 1 10 20 30 40 50 60 70 80 0 0.01 1000 v dd = 5v reference output noise (0.1hz to 10hz) (v dd = 1.8v, v ref = 1.2v) max5522 toc38 1s/div 100 v/div reference output noise (0.1hz to 10hz) (v dd = 5v, v ref = 3.9v) max5522 toc39 1s/div 100 v/div dac-to-dac crosstalk max5522 toc40 400 s/div outb ac-coupled 10mv/div outa 1v/div outb at full scale reference psrr vs. frequency max5522 toc36 frequency (khz) power-supply rejection ratio (db) 100 10 0.1 1 10 20 30 40 50 60 70 80 0 0.01 1000 v dd = 1.8v reference load transient (v dd = 5v) max5522 toc35 200 s/div refout sink current 100 a/div v ref 500mv/div 3.9v
max5522?ax5525 dual, ultra-low-power, 10-bit, voltage-output dacs ______________________________________________________________________________________ 11 pin description pin max5522 max5523 MAX5524 max5525 name function 1111 cs active-low digital chip-select input 2222 sclk serial-interface clock input 3333 din serial-interface data input 4 4 refin reference input ? ? refout reference output 5, 11 5, 11 n.c. no connection. leave n.c. inputs unconnected (floating) or connected to gnd. 66 fbb channel b feedback input 5577 outb channel b analog voltage output 6688 v dd power input. connect v dd to a 1.8v to 5.5v power supply. bypass v dd to gnd with a 0.1? capacitor. 7799 gndgr ound 88 10 10 outa channel a analog voltage output 12 12 fba channel a feedback input ep ep exposed paddle exposed paddle. connect ep to gnd. 10-bit dac dac register outa refin gnd max5522 input register power- down control control logic and shift register 10-bit dac dac register outb sclk v dd din cs input register functional diagrams
max5522?ax5525 dual, ultra-low-power, 10-bit, voltage-output dacs 12 ______________________________________________________________________________________ functional diagrams (continued) 10-bit dac 2-bit programmable reference dac register outa ref buf gnd max5523 refout input register power- down control control logic and shift register 10-bit dac dac register outb sclk v dd din cs input register 10-bit dac dac register outa refin gnd MAX5524 input register power- down control control logic and shift register 10-bit dac dac register outb fba fbb sclk v dd din cs input register
detailed description the max5522?ax5525 dual, 10-bit, ultra-low-power, voltage-output dacs offer rail-to-rail buffered voltage outputs. the dacs operate from a 1.8v to 5.5v supply and require only 5? (max) supply current. these devices feature a shutdown mode that reduces overall current, including the reference input current, to just 0.18? (max) the max5523/max5525 include an inter- nal reference that saves additional board space and can source up to 8ma, making it functional as a system reference. the 16mhz, 3-wire serial interface is com- patible with spi, qspi, and microwire protocols. when v dd is applied, all dac outputs are driven to zero scale with virtually no output glitch. the max5522/ max5523 output buffers are configured in unity gain and come in ?ax packages. the MAX5524/max5525 output buffers are configured in force sense allowing users to externally set voltage gains on the output (an output-amplifier inverting input is available). the MAX5524/max5525 come in 4mm x 4mm thin qfn packages. digital interface the max5522?ax5525 use a 3-wire serial interface that is compatible with spi/qspi/microwire protocols (figures 1 and 2). the max5522?ax5525 include a single, 16-bit, input shift register. data loads into the shift register through the serial interface. cs must remain low until all 16 bits are clocked in. the 16 bits consist of 4 control bits (c3?0), 10 data bits (d9?0) ( table 1), and 2 sub-bits (s1 and s0). d9?0 are the dac data bits and s1 and s0 are the sub-bits. the sub-bits must be set to zero for proper operation. following the control bits, data loads msb first, d9?0. the control bits c3?0 control the max5522?ax5525, as outlined in table 2. each dac channel includes two registers: an input reg- ister and a dac register. the input register holds input data. the dac register contains the data updated to the dac output. the double-buffered register configuration allows any of the following: ? loading the input registers without updating the dac registers ? updating the dac registers from the input registers ? updating all the input and dac registers simultaneously max5522?ax5525 dual, ultra-low-power, 10-bit, voltage-output dacs ______________________________________________________________________________________ 13 functional diagrams (continued) 10-bit dac 2-bit programmable reference dac register outa ref buf gnd max5525 refout input register power- down control control logic and shift register 10-bit dac dac register outb fba fbb sclk v dd din cs input register
max5522?ax5525 dual, ultra-low-power, 10-bit, voltage-output dacs 14 ______________________________________________________________________________________ t csw t css t cs0 t dh t cl t cs1 t csh t ch t ds sclk din cs c2 c1 s0 c3 figure 1. timing diagram 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 sclk c3 c2 c1 c0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 s1 s0 din control bits data bits sub-bits command executed cs figure 2. register loading diagram table 1. serial write data format sub-bits s1 to s0 must be set to zero for proper operation. control data bits msb lsb c3 c2 c1 c0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 s1 s0
max5522?ax5525 dual, ultra-low-power, 10-bit, voltage-output dacs ______________________________________________________________________________________ 15 table 2. serial-interface programming commands control bits input data sub-bits c3 c2 c1 c0 d9?0 s1 and s0 function 0000 xxxxxxxxxx 00 no operation; command is ignored. 0001 10-b it data 00 load input register a from shift register; dac registers unchanged; dac outputs unchanged. 0010 10-b it data 00 load input register b from shift register; dac registers unchanged; dac outputs unchanged. 00 11 command reserved. do not use. 01 00 command reserved. do not use. 01 01 command reserved. do not use. 01 10 command reserved. do not use. 01 11 command reserved. do not use. 1000 10-b it data 00 load dac registers a and b from respective input registers; dac outputs a and b updated; max5523/max5525 enter normal operation if in standby or shutdown; max5522/MAX5524 enter normal operation if in shutdown. 1001 10-b it data 00 load input register a and dac register a from shift register; dac output a updated; load dac register b from input register b; dac output b updated; max5523/max5525 enter normal operation if in standby or shutdown; max5522/MAX5524 enter normal operation if in shutdown. 1010 10-b it data 00 load input register b and dac register b from shift register; dac output b updated; load dac register a from input register a; dac output a updated; max5523/max5525 enter normal operation if in standby or shutdown; max5522/MAX5524 enter normal operation if in shutdown. 10 11 command reserved. do not use. 1100 d9, d8, xxxxxxxx 00 max5523/max5525 enter standby*, max5522/MAX5524 enter shutdown. for the max5523/max5525, d9 and d8 configure the internal reference voltage (table 3). 1101 d9, d8, xxxxxxxx 00 max5522?ax5525 enter normal operation; dac outputs reflect existing contents of dac registers. for the max5523/max5525, d9 and d8 configure the internal reference voltage (table 3). 1110 d9, d8, xxxxxxxx 00 max5522?ax5525 enter shutdown; dac outputs set to high impedance. for the max5523/max5525, d9 and d8 configure the internal reference voltage (table 3). 1111 10-b it data 00 load input registers a and b and dac registers a and b from shift register; dac outputs a and b updated; max5523/max5525 enter normal operation if in standby or shutdown; max5522/MAX5524 enter normal operation if in shutdown. x = don? care. * standby mode can be entered from normal operation only. it is not possible to enter standby mode from shutdown.
power modes the max5522?ax5525 feature two power modes to conserve power during idle periods. in normal opera- tion, the device is fully operational. in shutdown mode, the device is completely powered down, including the internal voltage reference in the max5523/max5525. the max5523/max5525 also offer a standby mode in which all circuitry is powered down except the internal voltage reference. standby mode keeps the reference powered up while the remaining circuitry is shut down, allowing it to be used as a system reference. it also helps reduce the wake-up delay by not requiring the ref- erence to power up when returning to normal operation. shutdown mode the max5522?ax5525 feature a software-program- mable shutdown mode that reduces the supply current and the interface input-current to 0.18? (max). writing an input control word with control bits c[3:0] = 1110 ( table 2) places the device in shutdown mode. in shut- down, the max5522/MAX5524 reference input and dac output buffers go high impedance. placing the max5523/ max5525 into shutdown turns off the internal reference and the dac output buffers go high impedance. the seri- al interface still remains active for all devices. table 2 shows several commands that bring the max5522?ax5525 back to normal operation. the power-up time from shutdown is required before the dac outputs are valid. note: for the max5523/max5525, standby mode can- not be entered directly from shutdown mode. the device must be brought into normal operation first before entering standby mode. standby mode (max5523/max5525 only) the max5523/max5525 feature a software-program- mable standby mode that reduces the typical supply current to 3? (max). standby mode powers down all circuitry except the internal voltage reference. place the device in standby mode by writing an input control word with control bits c[3:0] = 1100 ( table 2). the internal reference and serial interface remain active while the dac output buffers go high impedance. for the max5523/max5525, standby mode cannot be entered directly from shutdown mode. the device must be brought into normal operation first before entering standby mode. to enter standby from shutdown, issue the command to return to normal operation followed immediately by the command to go into standby. table 2 shows several commands that bring the max5523/max5525 back to normal operation. when transitioning from standby mode to normal operation, only the dac power-up time is required before the dac outputs are valid. reference input the max5522/MAX5524 accept a reference with a volt- age range extending from 0 to v dd . the output voltage (v out ) is represented by a digitally programmable volt- age source as: v out = (v ref x n / 256) x gain where n is the numeric value of the dac? binary input code (0 to 1023), v ref is the reference voltage, gain is the externally set voltage gain for the MAX5524, and gain is one for the max5522. in shutdown mode, the reference input enters a high- impedance state with an input impedance of 2.5g ? (typ). reference output the max5523/max5525 internal voltage reference is software configurable to one of four voltages. upon power-up, the default reference voltage is 1.214v. configure the reference voltage using d8 and d9 data bits ( table 3) when the control bits are as follows c[3:0] = 1100, 1101, or 1110 ( table 2). v dd must be kept at a minimum of 200mv above v ref for proper operation. max5522?ax5525 dual, ultra-low-power, 10-bit, voltage-output dacs 16 ______________________________________________________________________________________ table 3. reference output voltage programming d7 d6 reference voltage (v) 00 1.214 01 1.940 10 2.425 11 3.885
max5522?ax5525 dual, ultra-low-power, 10-bit, voltage-output dacs ______________________________________________________________________________________ 17 applications information 1-cell and 2-cell circuits see figure 3 for an illustration of how to power the max5522?ax5525 with either one lithium-ion battery or two alkaline batteries. the low current consumption of the devices make the max5522?ax5525 ideal for battery-powered applications. programmable current source see the circuit in figure 4 for an illustration of how to configure the MAX5524/max5525 as a programmable current source for driving an led. the MAX5524/ max5525 drive a standard npn transistor to program the current source. the current source (i led ) is defined in the equation in figure 4. refin MAX5524 max6006 (1 a, 1.25v shunt reference) gnd +1.25v 0.01 f 536k ? v dd dac vout n dac is the numeric value of the dac input code. v out (1.22mv / lsb) 1.8v v alkaline 3.3v 2.2v v lithium 3.3v v out = v refin n dac 1024 0.1 f figure 3. portable application using two alkaline cells or one lithium coin cell r 2n3904 n dac is the numeric value of the dac input code. i led refin led 1/2 MAX5524 v+ dac vout i led = v refin n dac 1024 r fb figure 4. programmable current source driving an led r fb n dac is the numeric value of the dac input code. i t refin 1/2 MAX5524 dac vout v out = v bias + (i t r) v out v bias transducer v bias = v refin n dac 1024 figure 5. transimpedance configuration for a voltage-biased current-output transducer
max5522?ax5525 voltage biasing a current-output transducer see the circuit in figure 5 for an illustration of how to configure the MAX5524/max5525 to bias a current-out- put transducer. in figure 5, the output voltage of the MAX5524/max5525 is a function of the voltage drop across the transducer added to the voltage drop across the feedback resistor r. unipolar output figure 6 shows the MAX5524 in a unipolar output con- figuration with unity gain. table 4 lists the unipolar out- put codes. bipolar output the MAX5524 output can be configured for bipolar operation as shown in figure 7. the output voltage is given by the following equation: v out_ = v refin x [(n a - 512) / 512] where n a represents the decimal value of the dac? binary input code. table 5 shows the digital codes (off- set binary) and the corresponding output voltage for the circuit in figure 7. configurable output gain the MAX5524/max5525 have force-sense outputs, which provide a connection directly to the inverting ter- minal of the output op amp, yielding the most flexibility. the advantage of the force-sense output is that specific gains can be set externally for a given application. the gain error for the MAX5524/max5525 is specified in a unity-gain configuration (op-amp output and inverting ter- minals connected), and additional gain error results from external resistor tolerances. another advantage of the force-sense dac is that it allows many useful circuits to be created with only a few simple external components. an example of a custom fixed gain using the MAX5524/ max5525 force-sense output is shown in figure 8. in this example, r1 and r2 set the gain for v outa . v outa = [(v refin x n a ) / 1024] x [1 + (r2 / r1)] where n a represents the numeric value of the dac input code. self-biased two-electrode potentiostat application see the circuit in figure 10 for an illustration of how to use the max5525 to bias a two-electrode potentiostat on the input of an adc. power supply and bypassing considerations bypass the power supply with a 4.7? capacitor in parallel with a 0.1? capacitor to gnd. minimize lengths to reduce lead inductance. if noise becomes an issue, use shielding and/or ferrite beads to increase isolation. for the thin qfn package, connect the exposed pad to ground. dual, ultra-low-power, 10-bit, voltage-output dacs 18 ______________________________________________________________________________________ table 4. unipolar code table (gain = +1) dac contents msb lsb analog output 1111 1111 1100 +v ref (1023/1024) 1000 0000 0100 +v ref (513/1024) 1000 0000 0000 +v ref (512/1024) = +v ref /2 0111 1111 1100 +v ref (511/1024) 0000 0000 0100 +v ref (1/1024) 0000 0000 0000 0v table 5. bipolar code table (gain = +1) dac contents msb lsb analog output 1111 1111 1100 +v ref (511/512) 1000 0000 0100 +v ref (1/512) 1000 0000 0000 0v 0111 1111 1100 -v ref (1/512) 0000 0000 0100 -v ref (511/512) 0000 0000 0000 -v ref (512/512) = -v ref n a is the dac input code (0 to 1023 decimal). refin MAX5524 out_ fb_ v out = v refin n a 1024 dac figure 6. unipolar output circuit
layout considerations digital and ac transient signals coupling to gnd can create noise at the output. use proper grounding tech- niques, such as a multilayer board with a low-inductance ground plane. wire-wrapped boards and sockets are not recommended. for optimum system performance, use printed circuit (pc) boards. good pc board ground lay- out minimizes crosstalk between dac outputs, reference inputs, and digital inputs. reduce crosstalk by keeping analog lines away from digital lines. max5522?ax5525 dual, ultra-low-power, 10-bit, voltage-output dacs ______________________________________________________________________________________ 19 refin 1/2 MAX5524 out_ v out fb_ v+ 10k ? 10k ? v- dac figure 7. bipolar output circuit n daca is the numeric value of the dac a input code. refin dac v out1 v out1 = v refin n daca 1024 ( 1 + r2 ) r1 n dacb is the numeric value of the dac b input code. v out2 = v refin n dacb 1024 vouta 1/2 MAX5524 fba dac v out2 voutb fbb r2 r1 figure 8. separate force-sense outputs create unity and greater-than-unity dac gains using the same reference h l fb w n dac is the numeric value of the dac input code. n pot is the numeric value of the pot input code. refin 1/2 MAX5524 max5401 sot-pot 100k ? dac vout 5ppm/ c ratiometric tempco 1.8v v dd 5.5v v out v out = v refin n dac 1024 ( 1 + 255 - n pot ) 255 sclk din cs2 cs1 figure 9. software-configurable output gain dac band gap to adc out refout ref 1/2 max5525 to adc to adc fb we sensor ce i f r f c l figure 10. self-biased two-electrode potentiostat application
max5522?ax5525 dual, ultra-low-power, 10-bit, voltage-output dacs 20 ______________________________________________________________________________________ chip information transistor count: 10,688 process: bicmos dac band gap to adc outa refout max5525 to adc ref fba we sensor ce i f r f c l dac outb ref fbb figure 11. driven two-electrode potentiostat application 12 fba 11 n.c. 10 outa 45 n.c. 6 fbb 1 2 sclk 3 9 8 7 din gnd v dd outb MAX5524 max5525 cs refin(MAX5524) refout(max5525) thin qfn top view pin configurations (continued)
max5522?ax5525 dual, ultra-low-power, 10-bit, voltage-output dacs ______________________________________________________________________________________ 21 24l qfn thin.eps b 1 2 21-0139 package outline 12,16,20,24l qfn thin, 4x4x0.8 mm package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .)
max5522?ax5525 dual, ultra-low-power, 10-bit, voltage-output dacs 22 ______________________________________________________________________________________ package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .) b 2 2 21-0139 package outline 12,16,20,24l qfn thin, 4x4x0.8 mm
max5522?ax5525 dual, ultra-low-power, 10-bit, voltage-output dacs maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 23 2004 maxim integrated products printed usa is a registered trademark of maxim integrated products. package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .) 8lumaxd.eps package outline, 8l umax/usop 1 1 21-0036 j rev. document control no. approval proprietary information title: max 0.043 0.006 0.014 0.120 0.120 0.198 0.026 0.007 0.037 0.0207 bsc 0.0256 bsc a2 a1 c e b a l front view side view e h 0.6?0.1 0.6?0.1 0 .50?0.1 1 top view d 8 a2 0.030 bottom view 1 6 s b l h e d e c 0 0.010 0.116 0.116 0.188 0.016 0.005 8 4x s inches - a1 a min 0.002 0.95 0.75 0.5250 bsc 0.25 0.36 2.95 3.05 2.95 3.05 4.78 0.41 0.65 bsc 5.03 0.66 6 0 0.13 0.18 max min millimeters -1.10 0.05 0.15 dim

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